M.I.T. researchers have successfully etched a 25 nanometer grid onto a piece of silicon, as NewScientist.com reports, presumably opening a way to pack transistors far more densely than ever before – but that’s only one hurdle out of the way.

The technique could help us keep track with Moore’s law, which states that the number of transistors we can fit on a chip will double every two years.

Doing this depends on our ability to keep reducing the size of the structures on electronic chips. Today the smallest features on most computer chips are about 65 nm in size, but the first 45-nm chips have begun rolling off production lines, and 32-nm chips have been made in the laboratory.

To make chips with more densely packed transistors, you have to cut ever finer designs on the silicon. However, the industry has long passed the point where what gets put onto the chip is smaller than a single wavelength of light, meaning that engineers and scientists need tricks to etch patterns. In this case, the researchers used 351 nm wavelength lasers and set up an interference pattern that provided the sub-wavelength sized lines that are much smaller than the 45 nm chips starting to enter the market.

Unfortunately, the industry has some other mammoth problems. Not only would engineers need to find ways to move beyond straight lines into creating electronic components on silicon, but they’d have to overcome all sorts of problems that creep up. At some point, the semiconductor industry crossed a line and entered the wild and wacky world of teeny tiny quantum dimensions, where all sorts of peculiar things happen, and what seem to be perfectly good chip designs crash when they get burned to silicon.

At 45nm, everything is about variability. The integrated circuit manufacturing process is inherently imperfect. Slight differences in temperatures, process-step durations, chemical concentrations (such as dopant levels) and so forth can result in small differences between wafers, between dies on the same wafer and between transistors on the same die.

As the critical dimensions of chip structures continue to shrink, even minute changes in the fabrication process can result in major deviations in the final chip in terms of speed, power, reliability and yield. When the thickness of the gate oxide was measured in microns (or large fractions thereof), small variations in the thickness of this oxide from one transistor to another had relatively little effect. But today, with gate oxide layers now only a few angstroms thick, even a slight variation in thickness results in a much larger percentage deviation.

The rough translation is “way hard,” and every mistake means another run through a multi-million-dollar manufacturing process to see if the fixes work. You can’t make an omelet without breaking a few eggs, but when one 45nm design runs $30 million plus, you have one expensive breakfast. Some estimate that design costs even at 32nm will average $75 million. I’d like that omelet with golden eggs, please.

It’s not just expensive, but hard. Intel is still having problems with 45 nm:

Intel advised retailers to simply swap their 45nm orders with 65nm dual-cores until further notice and until there are healthier volumes. Intel did ship a bit better quantity of 45nm dual and quad parts of the server side, but not too much on the desktop side.

That’s OK, AMD is finally supposed to be leaving 65nm behind. So 25nm is a long way off, and the electronics industry – and everything that depends on it – may have to reconcile to a change in Moore’s Law: the number of transistors on a chip doubles … some day.

45nm “Penryn” Wafer image courtesy of Intel

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